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? semiconductor components industries, llc, 2003 march, 2003 - rev. 5 1 publication order number: ncp1501/d ncp1501, ncp1502 advance information dual mode pwm/linear buck regulator the ncp150x is a dual mode regulator that operates either as a pwm buck converter or as a low drop out linear regulator. if a synchronization signal is present, the ncp150x operates as a current mode pwm converter with synchronous rectification. the synchronization signal allows the user to control the location of the spurious frequency noise generated by a pwm converter. linear mode is active when a synchronization signal is not present. the ncp150x configuration allows an efficient high power operation and low noise during system sleep modes. features ? synchronous rectification for higher efficiency in pwm mode ? linear mode operation for low noise output at low loads ? integrated mosfets and feedback circuits ? cycle by cycle current limit ? automatic switching between pwm and linear mode ? operating frequency range of 500 to 1000 khz ? thermal limit protection ? built-in slope compensation for current mode pwm converter ? fixed output voltages 1.05, 1.35, 1.57, 1.8 (ncp1501) 1.0, 1.3, 1.5, 1.9 (ncp1502) ? shutdown current consumption of 0.2 a typical applications ? cellular phones ? pdas ? pagers ? supplies for dsp cores ? portable applications figure 1. typical applications circuit c out ncp1501 8 7 6 5 1 2 3 4 shd syn v o lx cb0 cb1 gnd v in c in 10 h l 10 10 v bat v out ncp1502 8 7 6 5 1 2 3 4 micro8 (msop-8) dm suffix case 846a 8 1 1 8 x = 1 or 2 a = assembly location y = year w = work week marking diagram pin connections shd syn v o lx cb0 cb1 gnd v in device package shipping ordering information ncp1501dmr2 micro8 4000/tape & reel (top view) 150x ayw http://onsemi.com NCP1502DMR2 micro8 4000/tape & reel
ncp1501, ncp1502 http://onsemi.com 2 pin function descriptions pin # symbol pin description 1 shd enable pin for the ncp150x. this pin is active high. internal pull down resistor forces the part off if the pin is not connected on the board. 2 syn external synchronization signal pin. the device will operate in pwm mode if a clock signal is present. the pin must be pulled low to enter ldo mode. internal pull down resistor on pin. 3 v o feedback for the ncp150x. an internal mosfet is connected across v o and lx for ldo mode. 4 lx connection for the pass devices to the inductor. 5 v in input voltage to the ncp150x. 6 gnd ground connection for the device. 7 cb1 voltage selection bit. internal pull up resistor on pin. 8 cb0 voltage selection bit. internal pull down resistor on pin. maximum ratings rating symbol value unit maximum voltage all pins v max 5.5 v maximum operating voltage all pins v max 5.2 v thermal resistance, junction-to-air r ja 240 c/w operating ambient temperature range t a -30 to +85 c storage temperature range t stg -55 to +150 c junction operating temperature range t j -30 to +125 c electrical characteristics (v in = 3.6 v, v o = 1.57 v, t a = 25 c, f syn = 600 khz 50% duty cycle square wave for pwm mode; t a = -30 to 85 c for min/max values, unless otherwise noted.) characteristic symbol min typ max unit v cc pin quiescent current of switching mode, i out = 0 ma iq pwm - 140 - a quiescent current of ldo mode, i out = 0 ma iq ldo - 32 - a quiescent current, shd low iq off - 0.2 1.0 a input voltage range v in 2.7 - 5.2 v sync pin input voltage v sync -0.3 - v cc +0.3 v frequency operational range f sync 500 - 1000 khz minimum synchronization pulse width dc sync(min) - 30 - % maximum synchronization pulse width dc sync(max) - 70 - % sync ho voltage threshold v sync(h) - 920 1200 mv sync lo voltage threshold v sync(l) 400 830 - mv sync ho input current, v sync = 3.6 v i sync(h) - 1.8 - a sync lo input current, v sync = 0 v i sync(l) -0.5 0.005 - a output level selection pins input voltage v cb -0.3 - v cc +0.3 v cb0,1 ho voltage threshold v cb(h) - 910 1200 mv cb0,1 lo voltage threshold v cb(l) 400 850 - mv cb0,1 ho input current, cbx = 3.6 v i cb(h) - 1.8 - a cb0,1 lo input current, cbx = 0 v i cb(l) -0.5 0 - a
ncp1501, ncp1502 http://onsemi.com 3 electrical characteristics (continued) (v in = 3.6 v, v o = 1.57 v, t a = 25 c, f syn = 600 khz 50% duty cycle square wave for pwm mode; t a = -30 to 85 c for min/max values, unless otherwise noted.) characteristic symbol min typ max unit shutdown pin input voltage v shd -0.3 - v cc +0.3 v shd ho voltage threshold v shd(h) - 920 1200 mv shd lo voltage threshold v shd(l) 400 850 - mv shd ho input current, shd = 3.6 v i shd(h) - 1.8 - a shd lo input current, shd = 0 v i shd(l) -0.5 0 - a feedback pin input voltage v fb -0.3 - v cc +0.3 v input current, v fb = 1.8 v i fb - 8.5 - a pwm mode characteristics switching p-fet current limit i lim - 800 - ma duty cycle dc - - 100 % minimum on time t on(min) - 100 - nsec r ds(on) switching n-fet p-fet r ds(on) - - 0.7 0.6 - - ohms switching p-fet and n-fet leakage current i leak - 0.01 10 a output over voltage threshold v o - 5.0 - % ncp1501 output voltage accuracy, i out = 10 to 120 ma, v out(set) = 1.05 v 1.35 v 1.57 v 1.8 v v out 1.018 1.309 1.523 1.740 1.050 1.350 1.570 1.800 1.082 1.391 1.617 1.860 v ncp1502 output voltage accuracy, i out = 10 to 120 ma, v out(set) = 1.0 v 1.3 v 1.5 v 1.9 v v out 0.970 1.260 1.450 1.843 1.000 1.300 1.500 1.900 1.030 1.340 1.550 1.957 v load transient response, 10 to 100 ma load step v out - - 50 mv line transient response, i out = 100 ma, 3.0 to 3.6 v in line step v out - 5 - mv pp ldo mode characteristics r ds(on) ldo fet (inductor switch), lx to v out r ds(on) - 7.0 - ohms dropout voltage (limited by v in(min) = 2.5 v and v out(max) = 1.8 v) v in - v out - 0.7 - v ncp1501 output voltage accuracy, i out = 0.01 to 50 ma, v out(set) = 1.05 v 1.35 v 1.57 v 1.8 v v out 1.018 1.309 1.523 1.740 1.050 1.350 1.570 1.800 1.082 1.391 1.617 1.860 v ncp1502 output voltage accuracy, i out = 0.01 to 50 ma, v out(set) = 1.0 v 1.3 v 1.5 v 1.9 v v out 0.970 1.260 1.450 1.843 1.000 1.300 1.500 1.900 1.030 1.340 1.550 1.957 v
ncp1501, ncp1502 http://onsemi.com 4 figure 2. typical circuit with the internal schematic shd - + - + - reference softstart thermal sync detection and timing block output voltage program mux - shutdown linear control block q s r syn cb0 cb1 output voltage v o lx v cc input out out out slope compensation + mode select v ref + 5% v ref error amplifier ovp comparator pwm comparator pwm i limit out c2 ground voltage c1 component value manufacturer c1, c2 10 f, 6.3 v l tdk, llf4017-100 (i out = 300 ma) coilcraft, lpo4812-103mx (i out = 300 ma) coilcraft, 0805ps-103m (i out = 150 ma) tdk, nlc252018t-100 (i out = 100 ma) tdk, c2012x5r0j106m 10 h l q - + - + - +
ncp1501, ncp1502 http://onsemi.com 5 detailed operating description the buck regulator is a synchronous rectifier pwm regulator with integrated mosfets. this regulator has an ldo function for low power modes to conserve power and lower ripple voltage associated with pfm mode. the ncp150x does not contain an internal oscillator for the switching mode. the dual pwm/ldo mode is an exclusive patent pending circuit. the pwm clock is generated via an external clock signal on the synchronization pin. the operating frequency range for the pwm is 450 to 1000 khz. the output current of the pwm is typically 100 ma with a guarantee of over 300 ma for the 2.5 to 5.2 input voltage range. if a synchronization pulse is not present, the ncp150x changes into the ldo mode. the ldo function assures the user of an extremely low output ripple voltage and greatly reduced quiescent current when the users system is in a sleep mode. internally to the ncp150x, the synchronization pin has a pull down resistor to force the part into ldo mode when a clock signal is not present. to place the ncp150x in ldo mode, the user must set the synchronization pin low. the ldo mode guarantees an output in excess of 50 ma. pins cb0 and cb1 control the output voltage selection. the four voltages are 1.05, 1.35, 1.57, 1.8 or 1.0, 1.3, 1.5, 1.9 volts. cb0 and cb1 contain pull down resistors internally to the ncp150x. the pull down resistors force the output of the converter to a fixed voltage if the pins are floating connections to the external circuit. the shutdown pin enables the operation of the device. the shutdown pin has an internal pull down resistor to force the ncp150x into the off mode if this pin is floating due to the external circuit. during startup, the ncp150x has a soft start function to limit fast dv/dt and eliminate overshoot on the output. figure 3. block diagram and circuit schematic of the ncp150x l1 v bat sync shd c in 10 dc/dc control ldo control q2 ea cb0 cb1 10 h lx fb v out c out 10 i lim q1 q3 the external components required are an input and an output 10 f ceramic capacitor and a 10 h inductor. pwm mode during normal operation, a synchronization pulse acts as the clock for the dc/dc controller. the rising edge of the clock pulls the gate of q1 low allowing the inductor to charge. when the current through q1 reaches either the current limit or feedback voltage reaches its limit, q1 will turn off and q2 will turn on. q2 replaces the free wheeling diode typically associated with buck converters. q2 will turn off when either a rising edge sync pulse is present or all the stored energy is depleted from the inductor. q3 remains off during this mode. the output voltage accuracy in the pwm mode is well within 3% of the nominal set value. an over voltage protection circuit is present in the pwm mode to limit the positive voltage spike due to fast load transient conditions. the pwm also has the ability to go to 100% duty cycle for transient conditions and low input to output voltage differentials. in pwm mode, each switching cycle has a guaranteed on-time of 100 ns. the ncp150x has two protection circuits that can eliminate the cycle. when tripped, the over voltage protection or the thermal shutdown overrides the gate drive of the high side mosfet. ncp150x contains a damping circuit for the inductor. the damping circuit is active during discontinuous switching mode. this circuit eliminates the oscillations in the inductor when it is depleted of its energy.
ncp1501, ncp1502 http://onsemi.com 6 figure 4. pwm circuit schematic sync v bat c1 10 c2 10 r3 r4 - + - + q2 v ref error amp latch q s r en - + ocp q1 l1 10 h v ref + 5% load i pfet r2 r1 comp ovp comp set ramp en ldo mode when the synchronization pulse is not present, the ncp150x operates as an ldo. the dc/dc control circuitry will relinquish control of q1 and turn off q2. the ldo control circuitry will turn on q3 as a bypass circuit to the inductor. q1 is the controlling pass device of the ldo that regulates the input to output voltage dropout. the ldo can source an output current in excess of 50 ma. figure 5. ldo circuit schematic sync v bat c1 10 c2 10 r3 r4 - + v ref error amp switch/invert out in en q1 l1 10 h load set ramp en q3
ncp1501, ncp1502 http://onsemi.com 7 voltage output selection the output voltage selection is accomplished via two external pins: cb0 and cb1. if cb0 and cb1 pins are left floating by the external circuit, the output voltage will default to 1.35/1.3 v. the corresponding voltages are as follows. ncp1501 ncp1502 cb0 cb1 v out (v) v out (v) 0 0 1.05 1.0 0 1 1.35 1.3 1 0 1.80 1.9 1 1 1.57 1.5 figure 6. transition waveforms from ldo to pwm mode v in 0 3.0 0 010 external sync signal internal clk signal time figure 7. power up and power down sequence 1.8 v 1.0 v 1.5 v 1.3 v v in shd v o cb0 cb1
ncp1501, ncp1502 http://onsemi.com 8 figure 8. waveforms during normal operation 198.0 201.0 204.0 207.0 210.0 213.0 3.6040 3.6000 3.5960 400 m 200 m 0.00 400 m 300 m 200 m 400 m 100 m -200 m 1.01 1.00 990 m 3.70 1.35 -1.00 time ( ) v in i pfet i l i nfet v o v lx
ncp1501, ncp1502 http://onsemi.com 9 applications information ncp150x is a dual mode pwm or ldo step down converter. this dual mode takes advantage of the best of each mode. there are three required external components: an input and output capacitor and an inductor. the pwm mode allows high efficiency for larger loads. a typical efficiency for an input of 3.6 volts and an output of 1.8 volts and 100 ma is over 90%. low r dson and synchronous rectification contained within the device contributes to the very high efficiency. as with other synchronous rectification devices, the ncp150x does not require an external diode to supplement the nfet during switching on or off. a synchronization pin allows the user to define the frequency noise spikes of the pwm. the duty cycle of the synchronization signal must be within the range of 30% to 70%. the rising edge of the signal from the synchronization pin acts as the oscillator signal to set the latch and reset the ramp compensation signal. an over voltage protection circuit ensures the output will respond properly to fast transients from large to small loads. the ncp150x allows the pwm mode to enter a 100% duty cycle for fast load transient conditions and low input to output voltage differentials. the ldo mode is effective during low load conditions by lowering the quiescent current and reducing the output ripple voltage associated with pwm converters entering pfm mode. ncp150x enters the ldo mode when a synchronization signal is not present. it is recommended to pull the synchronization signal low for ldo mode. figure 9. typical operating schematic c out ncp1501 8 7 6 5 1 2 3 4 shd syn v o lx cb0 cb1 gnd v in c in 10 h l 10 10 v bat v out c in , c out : 10 f ceramic, c2012x5r0j106m (tdk) l: 10 h, llf4017-100 (tdk) ncp1502 figure 10. input current versus voltage for the shutdown pin 5 4 3 2 1 0 v shd (v) i shd ( a) 2.5 2 1.5 1 0.5 0 v cc = 3.6 v t a = 25 c figure 11. input current versus voltage for the synchronization pin 4 3 2 1 0 v syn (v) i syn ( a) 2 1.8 1.2 1 0.2 0 v cc = 3.6 v t a = 25 c 0.4 0.6 0.8 1.4 1.6
ncp1501, ncp1502 http://onsemi.com 10 v th low figure 12. input current versus voltage for the cb pins 4 3 2 1 0 v cb (v) i cb ( a) 2.5 2 1.5 1 0.5 0 v cc = 3.6 v t a = 25 c figure 13. input current versus voltage for the feedback pin 2 1.5 1 0.5 0 v fb (v) i fb ( a) 8 7 4 3 0 -1 v cc = 3.6 v t a = 25 c pwm mode 1 2 5 6 figure 14. v cc input voltage versus cb threshold 6 5 4 3 2 v cc (v) v cb(threshold) (v) 0.93 0.89 0.88 0.85 0.84 t a = 25 c ldo mode figure 15. transition level of cb pins 1.4 0.6 0.4 0.2 0 v cb (v) v out (v) 1.55 1.5 1.4 1.25 v cc = 3.6 v t a = 25 c ldo mode 1.3 1.35 1.45 figure 16. input voltage versus shutdown voltage figure 17. output voltage versus shutdown pin voltage 0.87 0.86 0.92 0.91 0.90 v th high 1.2 1.0 0.8 6 5 4 3 2 v cc (v) v cb(threshold) (v) 0.93 0.89 0.88 0.85 0.84 t a = 25 c ldo mode 1.4 0.6 0.4 0.2 0 v cb (v) v out (v) 1.5 t a = 25 c ldo mode 0 0.87 0.86 0.92 0.91 0.90 v shd high 1.2 1.0 0.8 v shd low v shd decreasing v shd increasing
ncp1501, ncp1502 http://onsemi.com 11 figure 18. output voltage versus input v cc in pwm mode 6 3 2 1 0 v cc (v) v out (v) 2.1 1.9 1.3 0.3 -0.5 t a = 25 c pwm mode figure 19. output voltage versus input v cc in ldo mode 5 4 -0.3 -0.1 0.1 1.1 0.5 0.7 0.9 1.7 1.5 6 3 2 1 0 v in (v) v out (v) 2 1.8 1.2 0.2 -0.6 t a = 25 c ldo mode 5 4 -0.4 -0.2 0 1 0.4 0.6 0.8 1.6 1.4 1.8 v out 1.3 figure 20. efficiency versus output current 300 250 200 150 100 50 0 i out , output current (ma) efficiency (%) 95 90 85 80 75 70 1.0 1.5 v cc = 3.6 v freq = 600 khz t a = 25 c see figure 9 for circuit
ncp1501, ncp1502 http://onsemi.com 12 sync v out lx sync v out lx v out v in v out v in v out i out v out i out
ncp1501, ncp1502 http://onsemi.com 13 160 140 120 100 80 200 180 60 40 20 2.0 n v in = 3.6 v out = 1.5 load = 15 f = 1.0 mhz start 0 hz 1.0 mhz stop 10 mhz 800 700 600 500 400 1.0 m 900 300 200 100 10 n v in = 3.6 v out = 1.5 load = 15 f = 600 khz start 0 hz 1.0 mhz stop 10 mhz 800 700 600 500 400 1.0 m 900 300 200 100 10 n v in = 3.6 v out = 1.5 load = 15 f = 600 khz start 0 hz 1.0 mhz stop 10 mhz figure 21. v rms versus frequency figure 22. v rms versus frequency figure 23. noise versus frequency 160 140 120 100 80 200 180 60 40 20 2.0 n v in = 3.6 v out = 1.5 load = 15 f = 1.0 mhz start 0 hz 1.0 mhz stop 10 mh z figure 24. v rms versus frequency 805.4 v 129.3 v 854.3 nv hz 130.3 nv hz
ncp1501, ncp1502 http://onsemi.com 14 package dimensions micro8 (msop-8) dm suffix case 846a-02 issue f s b m 0.08 (0.003) a s t dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c --- 1.10 --- 0.043 d 0.25 0.40 0.010 0.016 g 0.65 bsc 0.026 bsc h 0.05 0.15 0.002 0.006 j 0.13 0.23 0.005 0.009 k 4.75 5.05 0.187 0.199 l 0.40 0.70 0.016 0.028 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. 846a-01 obsolete, new standard 846a-02. -b- -a- d k g pin 1 id 8 pl 0.038 (0.0015) -t- seating plane c h j l on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. typicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 2-9-1 kamimeguro, meguro-ku, tokyo, japan 153-0051 phone : 81-3-5773-3850 on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. ncp1501/d micro8 is a trademark of international rectifier. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303-675-2175 or 800-344-3860 toll free usa/canada fax : 303-675-2176 or 800-344-3867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 800-282-9855 toll free usa/canada

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